1. Field of the Invention
The present invention relates to a method of making a semiconductor, and more particularly to an improvement in making a highly efficient MOS electrode effect transistor.
2. Description of the Related Art
The first problem which arises with the recent miniaturization and higher efficiency of MOS electrode effect transistors is how to suppress the short channel effect. A gate mounted MOS electrode effect transistor technique has been proposed.
This technique suppresses the short channel effect by burrowing down into the silicon substrate in the channel area and virtually increasing the channel length, and furthermore improves the hot carrier resistance by moving the channel area from the source and drain parts.
FIGS. 1A and 1B show a processing flow of this technique. This is a cross sectional view of an N channel MOS transistor formed on the silicon substrate. As shown in FIG. 1A, a LOCOS oxide film 2 for separating elements is formed on the silicon substrate 1, and then a shallow trench 3 is formed in the channel area.
A gate oxide film 4 is then formed on the surface of the substrate including an inner part of the trench with the aid of a rapid thermal technique using an oxide diffusing furnace. In this connection, the LOCOS oxide film 4 is formed with a thickness of 400 to 500 nm and the gate oxide film is formed with a thickness of 10 to 20 nm.
Also in this event, boron ions are input in order to control the threshold voltage Vth.
Furthermore, as shown in FIG. 1B, N.sup.+ polysilicon films of a 200 to 400 nm thickness are deposited in trench 3 and on the surface of the substrate by CVD. Then, polysilicon is processed with the aid of an existing dry etching technique to form a gate electrode 5 of a MOS transistor.
Then, N.sup.+ ions are input into the MOS transistor and a source diffusion zone 6 and a drain diffusion zone 7 are formed. Then, the source diffusion zone 6 and the drain diffusion zone 7 are activated by the thermal processing and furthermore, each electrode is formed using the existing wiring technique (not shown). The MOS transistor is formed according to the procedure described above.
However, since it is necessary to fit the positions of electrode edges and the shallow trench 3 in the case of processing the gate electrode as shown in FIG. 1B, there is a possibility that the effective gate length L.sub.eff changes for the margin. Therefore, there has been a problem that an increase of a scattering of device characteristics and an improvement of the integration factor are prevented.